It is difficult to test very large scale integrated (VLSI) circuits. Nevertheless, it is essential to verify that such circuits function properly. The internal clock is one of the most important components of any synchronous VLSI circuit. A fully controllable integrated circuit internal clock is very important when debugging a VLSI circuit. By manipulating the internal clock in different ways, the circuit can be controlled to run in different modes and at different speeds during debug operations. These modes can be used either on a tester or in a system environment. Critical information about the state of the integrated circuit is obtained from clock manipulation of this type.
Integrated circuit internal clocks are commonly operated in accordance with a boundary scan test method. In the boundary scan test method, test data is serially loaded into locations within the integrated circuit and then the integrated circuit executes logical operations on the serially loaded data. The resultant output data is then verified for accuracy. The most prevalent boundary scan test method is described in "IEEE Standard Test Access Port and Boundary-Scan Architecture", IEEE STD 1149.1-1990 (referred to herein as IEEE 1149).
In IEEE 1149, it is specified that the clock must be capable of being stopped indefinitely in a selected state, without causing any change to the state of the test logic. The clock is stopped, for example, when a test system needs to fetch data from backup memory.
As VLSI circuits grow in size and increase in speed, the length of the signal distribution network that a clock signal must traverse also grows. In some cases, a clock signal phase displacement of over one-half cycle can exist between the input node and the output node of the signal distribution network. In such a case, it is difficult to coordinate a stop clock command with a clock signal. If such coordination cannot be insured, then the clock signal cannot be deterministicly stopped at a selected signal transition. As a result, it is difficult to capture certain error states in an integrated circuit. Thus, debugging operations are compromised.
In view of the foregoing, it would be highly desirable to provide a control circuit to deterministicly stop an integrated circuit internal clock. More particularly, it would be highly desirable to provide such a control circuit for integrated circuits with signal distribution networks with a clock signal phase displacement of over one-half cycle.